entity alu_tb is
end;

library ieee;				
use ieee.std_logic_1164.all;

architecture bench of alu_tb is

  signal testa3,testa2,testa1,testa0: STD_LOGIC;
  signal testb3,testb2,testb1,testb0: STD_LOGIC;
  signal aeqb,agtb,altb: STD_LOGIC;

begin

  comb_1: entity work.comb_ckt port map (testa3, testa2, testa1, testa0, testb3, testb2, testb1, testb0 , aeqb, agtb, altb);

  stim_proc: process
   begin
        -- A < B    
        testa3 <='0';
        testa2 <='1';
        testa1 <='0';
        testa0 <='1';
        
        testb3 <='1';
        testb2 <='0';
        testb1 <='1';
        testb0 <='0';
        
        wait for 10 ns;
        
        -- A > B
        
        testa3 <='1';
        testa2 <='0';
        testa1 <='1';
        testa0 <='0';
        
        testb3 <='0';
        testb2 <='1';
        testb1 <='0';
        testb0 <='1';
        
        wait for 10 ns;
        
        -- A = B
        
        testa3 <='1';
        testa2 <='0';
        testa1 <='1';
        testa0 <='0';
        
        testb3 <='1';
        testb2 <='0';
        testb1 <='1';
        testb0 <='0';
        
        wait for 10 ns;
        
        wait;

   end process;

end bench;
